SIA414DJ-T1-GE3

spice model, SC70-6, 0.57 V, n-channel vertical DMOS, Macro Model, Level 3 MOS

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PartNumber:: SIA414DJ-T1-GE3

Brand:: Vishay Siliconix - Vishay | Pack: SC | D/C: 10+

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Products Upload time: 2011-08-04

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Product Summary

The SIA414DJ-T1-GE3 attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The SIA414DJ-T1-GE3 is extracted and optimized over the -55 to 125℃ temperature ranges under the pulsed 0-V to 4.5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values of SIA414DJ-T1-GE3 are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.

Parametrics

SIA414DJ-T1-GE3 absolute maximum ratings: (1)Gate Threshold Voltage: 0.57 V at VDS = VGS, ID = 250 μA; (2)On-State Drain Currenta: 423 A at VDS ≤ 5 V, VGS = 4.5 V; (3)Drain-Source On-State Resistancea: 0.009 Ω at VGS = 4.5 V, ID = 9.7 A, 0.011 Ω at VGS = 2.5 V, ID = 9 A, 0.013 Ω at VGS = 1.8 V, ID = 8.1 A; (4)Forward Transconductance: 49 S at VDS = 6 V, ID = 9.7A; (5)Input Capacitance: 1872 pF; (6)Output Capacitance: 608 pF; (7)Reverse Transfer Capacitance: 447 pF at VDS = 4 V, VGS = 0 V, f = 1 MHz; (8)Gate-Source Charge: 2.5 nC; (9)Gate-Drain Charge: 6.5 nC at VDS = 4 V, VGS = 4.5 V, ID = 10 A.

Features

SIA414DJ-T1-GE3 features: (1)N-Channel Vertical DMOS; (2)Macro Model (Subcircuit Model); (3)Level 3 MOS; (4)Apply for both Linear and Switching Application; (5)Accurate over the -55 to 125℃ Temperature Range; (6)Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics.