Product Summary

The K4H561638F-UCB3 is a 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 4/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the K4H561638F-UCB3 to be useful for a variety of high performance memory system applications.

Parametrics

K4H561638F-UCB3 absolute maximum ratings: (1)Voltage on any pin relative to VSS, VIN, VOUT: -0.5 to 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS, VDD, VDDQ: -1.0 to 3.6 V; (3)Storage temperature, TSTG: -55 to +150℃; (4)Power dissipation, PD: 1.5 W; (5)Short circuit current, IOS: 50 mA.

Features

K4H561638F-UCB3 features: (1)Double-data-rate architecture; two data transfers per clock cycle; (2)Bidirectional data strobe L(U)DQS; (3)Four banks operation; (4)Differential clock inputs(CK and CK); (5)DLL aligns DQ and DQS transition with CK transition; (6)MRS cycle with address key programs: Read latency 2, 2.5 (clock); Burst length (2, 4, 8); Burst type (sequential & interleave); (7)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (8)Data I/O transactions on both edges of data strobe; (9)Edge aligned data output, center aligned data input; (10)LDM,UDM for write masking only (x16); (11)Auto & Self refresh; (12)7.8us refresh interval(8K/64ms refresh); (13)Maximum burst refresh cycle : 8; (14)66pin TSOP II Pb-Free package; (15)RoHS compliant.

Diagrams

K4H561638F-UCB3 block diagram

K4H561638H-UCCC
K4H561638H-UCCC

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Negotiable 
K4H561638H-UCA2
K4H561638H-UCA2

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Negotiable 
K4H561638F-UCCC
K4H561638F-UCCC

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Negotiable 
K4H561638F-UCC4
K4H561638F-UCC4

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Negotiable 
K4H561638F-LB3
K4H561638F-LB3

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Negotiable 
K4H561638F-LB0
K4H561638F-LB0

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Data Sheet

Negotiable